1. Field of the Invention
The present invention relates to a circuit structure and a layout method thereof, and more particularly to a semiconductor circuit structure wherein the circuit structure thereof can avoid damaging from stresses, and a layout method thereof.
2. Description of the Related Art
For increasing the integrated level of the semiconductor, circuit patterns in multi-layers are designed to increase the amount of elements held in a single chip. The circuit patterns employ metal line structures, such as plugs or contacts, to be connected with each other for forming a whole loop. Furthermore, for not contacting the circuit patterns in the multi-layers with each other, which do not connect the metal lines, dielectric layers are generally formed between the circuit patterns in the multi-layers to separate the circuit patterns.
FIG. 1 is a schematic view of a conventional semiconductor circuit structure. Referring to FIG. 1, the semiconductor circuit structure 100 mainly includes a substrate 110 and a plurality of circuit patterns 120 disposed on the substrate 110. Since a position distribution of the circuit patterns 120 are determined by the semiconductor manufacturing standards and the property of the circuit structure, distances between the circuit patterns 120 are different.
However, when the distances between the adjacent circuit patterns 120 are too large, that is, a great insulating area 130 is formed between the adjacent circuit patterns 120, stresses born by the semiconductor circuit structure 100 in manufacturing are apt to concentrate at junctions of the insulating area 130 and the circuit patterns 120, such that the circuit patterns 120 are apt to be disrupted or distorted.